A silicon carbide vertical field effect transistor (see, e.g., Paten Document 1) such as a vertical MOS field effect transistor (MOSFET) is conventionally used with a semiconductor device as a switching device formed on a silicon carbide substrate. Although a silicon carbide vertical MOSFET is exemplarily illustrated and described as a silicon carbide vertical field effect transistor in this description, this is, of course, not a limitation of the present invention.
FIG 6 depicts a cross-sectional view of an N-channel MOSFET, which is a conventional silicon carbide (hereinafter abbreviated as “SiC”) field effect transistor.
An N-type SiC layer 2 is formed on a surface of an N-type SiC substrate 1; multiple P-type regions 3 are formed on a surface of the N-type SiC layer 2; an N-type source region 4 and a P-type contact region 5 are formed on a surface of the P-type region 3; and a source electrode 8 is formed on surfaces of the N-type source region 4 and the P-type contact region 5. A gate electrode 7 is formed via a gate insulating film 6 on surfaces of the P-type regions 3 and the N-type SiC layer 2 between the N-type source regions 5. A drain electrode 9 is formed on a back side.
FIG 7 is a cross-sectional view of another N-channel MOSFET formed by using a P-type SiC layer on a surface. The N-type SiC layer 2 is formed on a surface of the N-type SiC substrate 1 and multiple P-type regions 10 are formed on a surface of the N-type SiC layer 2. A P-type SiC layer 11 is further formed on the surface. An N-type region 12 is formed in the P-type SiC layer 11 on the N-type SiC layer 2 where the P-type region 10 is not formed; the N-type source region 4 and the P-type contact region 5 are formed on a surface of the P-type silicon carbide region 11; and the source electrode 8 is formed on surfaces of the N-type source region 4 and the P-type contact region 5. The gate electrode 7 is formed via the gate insulating film 6 on surfaces of the P-type regions 3 and the N-type silicon carbide layer between the N-type source regions 5. The drain electrode 9 is formed on the back side.
In the MOSFETs of the structures depicted in FIGS. 6 and 7, and if voltage less than or equal to a gate threshold value is applied to the gate electrode 7 while positive voltage is applied to the drain electrode 9 relative to the source electrode 8, PN-junction between the P-type region 3 and the N-type SiC layer 2, or the P-type SiC layer 11 and the N-type region 12 is inversely-biased and therefore, no current flows.
On the other hand, if voltage greater than or equal to the gate threshold value is applied to the gate electrode 7, the formation of an inversion layer on the surface of the P-type region 3 or the P-type SiC layer 11 immediately below the gate electrode 7 causes current to flow and therefore, the switching operation of the MOSFET can be achieved by the voltage applied to the gate electrode 7.
However, if high voltage is applied to the drain electrode, particularly when the MOSFET is turned off, high voltage is applied to the drain electrode. In this case, if a large electric field is applied to the gate insulating film, insulation breakdown of the gate insulating film may occur or the reliability of the gate insulating film may significantly be reduced.
Patent Document 1: Japanese Laid-Open Patent Publication No. H11-121748